In US Patent Publication US 2004/0042292 A1 Sakata et al. disclose a write operation of a MRAM, where a current necessary for inverting magnetization of an MTJ element has to be passed through a data line resulting in large current consumption. The write operation includes comparing input data with read data read from a memory cell array and encoding the input data to form write data using a data encoder. Also disclosed is the decoding read data using a data decoder to form output data. In a nonvolatile semiconductor memory the number of bits to be written during the write operation is reduced, and the current consumption is also said to be reduced.
In U.S. Pat. No. 6,633,951 Cohen discloses a method and apparatus for reducing the power needed in a computing system to refresh dynamic random access memory. In one embodiment data to be stored to DRAM is evaluated one word at a time. For each eight-bit data word, if the number of ones is more than four, each bit of the data word is inverted and a data inversion indicator bit is set to a logic one, to indicate that the data has been inverted. This allows for the data to be stored accurately with the minimum number of ones present. Due to the power required to refresh ones stored in DRAM, storing a minimum number of ones reduces power consumption. A read of the data determines if the data had been inverted upon storage and, if so, the read data is reverted to its original form.
In U.S. Pat. No. 5,873,112 Norman discloses a method and system in which X-bit packets of bits (where X is an integer) are encoded to generate X-bit packets of encoded bits for writing to erased cells of a flash memory array, where less power is consumed to write a bit having a first value to an erased cell than to write a bit having a second value to the cell. A count signal is generated for each packet of raw bits indicating the number of bits of the packet having the first (or second) value, the count signal is processed to generate a control signal which determines an encoding for the packet, and the raw bits of the packet are encoded according to a scheme determined by the control signal. Each erased cell may be indicative of the binary value “1”, and the count signal is compared to a reference value (indicative of X/2) to generate a control signal determining whether the packet should undergo polarity inversion, and the packet is inverted (or not inverted) depending on the value of the control signal. The count signal can be generated for each packet of bits to be written to erased cells of an array (where the count signal indicates the number of bits in the packet having a particular value), and each packet is encoded in a manner determined by the corresponding count signal to reduce the power needed to write the encoded bits to the erased cells. Flag bits indicative of the encoding of each packet are generated, and the flag bits (as well as the encoded packets) are stored in cells of the flash memory array.
Other techniques for controlling memory power consumption are disclosed in IBM Technical Disclosure Bulletin Vol. 30, No. 1, June 1987, “Power Reduction Scheme with Data-Dependent Write”, pgs. 304-305; IBM Technical Disclosure Bulletin 11-89, “Reduced Power for High Performance Memory”, pgs. 415-416; and in IEEE publication “A High Performance Modular Embedded ROM Architecture”, Marcello Duhalde et al. (1995), pgs. 1057-1060.
Improvements to these conventional techniques are needed to even further reduce power consumption, and the resulting heat load generated by power consumption, in currently available and future data storage devices and systems.